Modern wireless systems keep reaching for higher frequencies to satisfy the growing demand for faster data transfer, and the 300-GHz band — near the lower end of the terahertz range — is a leading candidate for sixth-generation (6G) wireless because it can support very high data rates while minimizing atmospheric attenuation. The catch is that radio waves at these frequencies suffer severe path loss, making signal transmission over practical distances extremely difficult.

Phased-array transceivers, which combine multiple antenna elements and electronically steer a radio beam toward a receiver, can help recover that lost signal budget. But building compact, low-power phased arrays at 300 GHz — with antennas and bidirectional transmit-receive circuitry packed onto the same chip at half-wavelength spacing — has been an extremely difficult engineering problem.

A World-First Fully Integrated Array

A research team led by Professor Kenichi Okada at the Institute of Science Tokyo has built a two-dimensional phased-array transceiver capable of wireless communication in the terahertz band, entirely in complementary metal-oxide-semiconductor (CMOS) integrated-circuit technology — antennas, transmit and receive circuitry, all on one chip. The work, presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits in Honolulu, represents the world’s first fully integrated 2D phased array, including antennas, at frequencies above 200 GHz.

The transceiver operates across 240–270 GHz, with each element packing a phase shifter, frequency doubler, sub-terahertz injection-locked tripler, sub-harmonic mixer, and on-chip dipole antenna into a compact core area of just 0.30 mm², consuming only 26 mW per element. In communication tests, the transmitter supported a 16-Gbaud QPSK link while the receiver supported a 26-Gbaud QPSK link.

“This represents the first 300-GHz-band two-dimensional bi-directional phased-array transceiver with on-chip half-wavelength-spaced antennas implemented as a single all-CMOS chip. The low-power consumption and small chip area per element are particularly important because future terahertz wireless systems will require compact, scalable, and manufacturable front-end hardware.”

Kenichi Okada, Institute of Science Tokyo

Because the design relies on low-cost, mass-producible CMOS rather than exotic materials, the team believes it represents a meaningful step toward hardware that could actually be manufactured at scale, even though further development is needed before widespread deployment.

“The achievement may accelerate research related to 6G wireless systems and beyond, where compact phased arrays, beam steering, and low-power terahertz circuits will be essential for realizing ultra-high-speed wireless links.”

Kenichi Okada

The work was partially supported by Japan’s National Institute of Information and Communications Technology.

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The study, “A 240–270 GHz 4×4 Bi-Directional Phased-Array Transceiver with On-Chip Half-Wavelength-Spaced Array and Ultra-Low Power Consumption in 65-nm CMOS,” was presented at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits.